Shamika Chalse

DR. VISHWANATH KARAD MIT WORLD PEACE UNIVERSITY, PUNE • Computer

59 Circuits

lab assig 4 , 3-bit synchronous DOWN counter using JK flip flop

lab assig 4 , 3-bit synchronous DOWN counter using JK flip flop

lab assig 2 error 8:1 using 4:1 reduction

lab assig 2 error 8:1 using 4:1 reduction

74LS04 74LS153 74LS08

lab assig 2 decoder 4:1 practice

lab assig 2 decoder 4:1 practice

8:1 MUX using two 4:1 MUX ,reduction using Y=f(A,B,C)=summation(1,3,4,7)

8:1 MUX using two 4:1 MUX ,reduction using Y=f(A,B,C)=summation(1,3,4,7)

74LS04 74LS153 74LS32

lab assig 4 , 3 bit synchronous counter UP counter practice

lab assig 4 , 3 bit synchronous counter UP counter practice

lab assig 3 JK Flip Flop practice

lab assig 3 JK Flip Flop practice

lab assig 3 full adder using 3:8 decoder practice

lab assig 3 full adder using 3:8 decoder practice

lab assig 3 3 bit MOD 8 Up counter

lab assig 3 3 bit MOD 8 Up counter

lab assig 3 asynchronous down counter MOD 8 using Jk

lab assig 3 asynchronous down counter MOD 8 using Jk

lab assignment 2 8:1 using two 4:2 if (check for s0 s1 s2 pins)

lab assignment 2 8:1 using two 4:2 if (check for s0 s1 s2 pins)

74LS153 74LS04 74LS32

lab assig 2 4:1 mux practice

lab assig 2 4:1 mux practice

lab assig 2 sop using 4:1 mux for f=sumation(0,3)

lab assig 2 sop using 4:1 mux for f=sumation(0,3)

lab assig 2 pos using 4:1 mux f pie(A,B)=(0,3)

lab assig 2 pos using 4:1 mux f pie(A,B)=(0,3)

lab assig 1 binary to grey practice

lab assig 1 binary to grey practice

lab assig 1 gray to binary practice

lab assig 1 gray to binary practice

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