Shamika Chalse

DR. VISHWANATH KARAD MIT WORLD PEACE UNIVERSITY, PUNE • Computer

59 Circuits

Exp 4 3 bit synchronous down counter

Exp 4 3 bit synchronous down counter

Exp 4 3 –Bit Synchronous UP counter

Exp 4 3 –Bit Synchronous UP counter

Exp 3 mod 5 asynchronous counter using JK flip flop

Exp 3 mod 5 asynchronous counter using JK flip flop

Exp 3 mod 8 asynchronous counter using jk flip flop

Exp 3 mod 8 asynchronous counter using jk flip flop

full adder using decoder

full adder using decoder

Exp 2 Q3 8:1 Multiplexer using two 4:1Multiplexers

Exp 2 Q3 8:1 Multiplexer using two 4:1Multiplexers

74LS153 74LS04 74LS32

Exp 2 Q1 4:1 MUX

Exp 2 Q1 4:1 MUX

Exp 2 mux 4:1 sop f(A,B)=SUMATION m(0,3)

Exp 2 mux 4:1 sop f(A,B)=SUMATION m(0,3)

Exp 2 mux 4:1 pos f(A,B)=(0,3)

Exp 2 mux 4:1 pos f(A,B)=(0,3)

4:1 mux sum carry

4:1 mux sum carry

Eor gate

Eor gate

Binary to Gray assig1

Binary to Gray assig1

Gray to binary assig1

Gray to binary assig1

3-Bit Up counter Assig4

3-Bit Up counter Assig4

J-K Flip-Flop - Copy

J-K Flip-Flop - Copy

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