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Hrishikesh Iyer
DR. VISHWANATH KARAD MIT WORLD PEACE UNIVERSITY, PUNE • Computer
24 Circuits
Full adder using TWO 8:1 MUXes (28/2/23)
Hrishikesh Iyer
0
0
Feb 26, 2023
74LS151
Half subtractor using logic gates(28/2/23)
Hrishikesh Iyer
0
0
Feb 26, 2023
74LS08
74LS86
74LS04
Half adder using gates (28/2/23)
Hrishikesh Iyer
0
0
Feb 26, 2023
74LS08
74LS86
MultiplexerTruthTable(31/1/23)
Hrishikesh Iyer
0
0
Jan 31, 2023
74LS151
MultiplexerPOS(31/1/23)
Hrishikesh Iyer
0
0
Jan 31, 2023
74LS151
MultiplexerSOP(31/1/23)
Hrishikesh Iyer
0
0
Jan 31, 2023
74LS151
HalfAdder(31/1/23) - Copy
Hrishikesh Iyer
0
0
Jan 31, 2023
74LS153
HalfAdder(31/1/23)
Hrishikesh Iyer
0
0
Jan 30, 2023
74LS153
Binary To Gray ; Gray to Binary
Hrishikesh Iyer
0
0
Jan 24, 2023
74LS86
Page 2
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2
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