Appus Devis

INDIAN INSTITUTE OF INFORMATION TECHNOLOGY KOTTAYAM • Computer

21 Circuits

De Morgan's Laws

De Morgan's Laws

74LS32 74LS04 74LS08

Gray to Binary converter

Gray to Binary converter

74LS04 74LS08 74LS11 74LS32

2's complement of 3 bit number

2's complement of 3 bit number

74LS04 74LS08 74LS32

F(A,B,C,D) using NAND gates

F(A,B,C,D) using NAND gates

S-R Latch using NOR gate

S-R Latch using NOR gate

Single Bit Comparator

Single Bit Comparator

74LS04 74LS08 74LS02

Half adder with NOR gate

Half adder with NOR gate

1:2 Demultiplexer

1:2 Demultiplexer

2 to 4 Decoder

2 to 4 Decoder

4:1 Multiplexer

4:1 Multiplexer

74LS04 74LS11 74LS32

2:1 MUX using basic gates

2:1 MUX using basic gates

74LS08 74LS32 74LS04

XNOR using basic gates

XNOR using basic gates

74LS04 74LS08 74LS32

NOR gate with OR and NOT gate - Copy

NOR gate with OR and NOT gate - Copy

NOR gate implementation with OR and NOT gate

NOR gate implementation with OR and NOT gate

74LS32 74LS04 74LS02

AND gate implementation using NOR gate

AND gate implementation using NOR gate

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