AND gate implementation using NOR gate

Appus
Appus Devis
• Created on Jun 16, 2021 • 0 • 0 • 2
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AND gate implementation using NOR gate
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Integrated Circuits Used

74LS02 74LS08

Procedure

  1. Connect GND Port to Pin-7 (Ground) of ICBase-1 (74LS02).
  2. Connect GND Port to Pin-7 (Ground) of ICBase-2 (74LS08).
  3. Connect VCC Port to Pin-20 (VCC) of ICBase-2 (74LS08).
  4. Connect VCC Port to Pin-20 (VCC) of ICBase-1 (74LS02).
  5. Connect Pin-2 (Input) of ICBase-1 (74LS02) to Input-15.
  6. Connect Pin-3 (Input) of ICBase-1 (74LS02) to Input-15.
  7. Connect Pin-6 (Input) of ICBase-1 (74LS02) to Input-14.
  8. Connect Pin-5 (Input) of ICBase-1 (74LS02) to Input-14.
  9. Connect Pin-18 (Input) of ICBase-1 (74LS02) to Pin-1 (Output) of ICBase-1 (74LS02).
  10. Connect Pin-17 (Input) of ICBase-1 (74LS02) to Pin-4 (Output) of ICBase-1 (74LS02).
  11. Connect Output-15 to Pin-19 (Output) of ICBase-1 (74LS02).
  12. Connect Pin-1 (Input) of ICBase-2 (74LS08) to Input-15.
  13. Connect Pin-2 (Input) of ICBase-2 (74LS08) to Input-14.
  14. Connect Output-14 to Pin-3 (Output) of ICBase-2 (74LS08).
  15. Add IC 74LS02 into ICBase-1 (74LS02).
  16. Add IC 74LS08 into ICBase-2 (74LS08).