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Saumiya Rajendran
DR. VISHWANATH KARAD MIT WORLD PEACE UNIVERSITY, PUNE • Computer
22 Circuits
E_55_Sequence Generator
Saumiya Rajendran
0
0
Sep 28, 2021
74LS76
74LS08
MOD 5 Asynchronous Up Counter
Saumiya Rajendran
0
0
Sep 24, 2021
74LS76
74LS00
FULL ADDER using Decoder
Saumiya Rajendran
0
0
Sep 22, 2021
74LS138
74LS20
8:1 MUX using 2 - 4:1 MUX
Saumiya Rajendran
0
0
Sep 22, 2021
74LS04
74LS32
74LS153
Half Adder using IC74LS153 - Copy
Saumiya Rajendran
0
0
Sep 22, 2021
74LS153
SOP and POS using 1 - 4:1 MUX
Saumiya Rajendran
0
0
Sep 22, 2021
74LS153
Half Adder using Logic Gates
Saumiya Rajendran
0
0
Sep 21, 2021
74LS86
74LS08
Full Adder using Logic Gates
Saumiya Rajendran
0
0
Sep 21, 2021
74LS86
74LS08
74LS32
E_55_Saumiya_Mod5_Uptown Counter
Saumiya Rajendran
0
0
Sep 1, 2021
74LS76
74LS00
E_55_Saumiya_Up Counter
Saumiya Rajendran
0
0
Sep 1, 2021
74LS76
Down Counter - Copy
Saumiya Rajendran
0
0
Sep 1, 2021
74LS76
E_55_Saumiya_Down Counter
Saumiya Rajendran
0
0
Sep 1, 2021
74LS76
Reduction Circuit - Copy
Saumiya Rajendran
0
0
Aug 25, 2021
74LS153
74LS04
E_55_Saumiya_4:1 MUX Reduction
Saumiya Rajendran
0
0
Aug 25, 2021
74LS153
74LS04
E_55_SAUMIYA _Full Adder - Design using Reduction
Saumiya Rajendran
0
0
Aug 25, 2021
74LS04
74LS153
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