To Design and Verify the operation BCD ripple counter using JK flip-flops

Step-by-Step Procedure

1. Click on 'Next' button to Add Two IC-74LS76 and IC-74LS00
2. Click on 'Next' button to Connect GND and VCC of both ICs
3. Click on 'Next' button to Connect J-0 to Vcc
4. Click on 'Next' button to Connect K-0 to Vcc
5. Click on 'Next' button to Connect PR-0 to Vcc
6. Click on 'Next' button to Connect CLOCK-0 to Automatic Clock Port
7. Click on 'Next' button to Connect Q-0 to LSB of 7-Seg Display
8. Click on 'Next' button to Connect Q-0 to CLOCK-1
9. Click on 'Next' button to Connect J-1 to Vcc
10. Click on 'Next' button to Connect K-1 to Vcc
11. Click on 'Next' button to Connect PR-1 to Vcc
12. Click on 'Next' button to Connect Q-1 to 7-Seg Display
13. Click on 'Next' button to Connect Q-1 to CLOCK-2 (CLOCK-1 of IC-2)
14. Click on 'Next' button to Connect J2 (J-1 of IC-2) to Vcc
15. Click on 'Next' button to Connect K2 (K-1 of IC-2) to Vcc
16. Click on 'Next' button to Connect PR-2 (PR-1 of IC-2) to Vcc
17. Click on 'Next' button to Connect Q-2 (Q-1 of IC-2) to 7-Seg Display
18. Click on 'Next' button to Connect Q-2 to CLOCK-3 (CLOCK-2 of IC-2)
19. Click on 'Next' button to Connect J3 (J-2 of IC-2) to Vcc
20. Click on 'Next' button to Connect K3 (K-2 of IC-2) to Vcc
21. Click on 'Next' button to Connect PR-3 (PR-2 of IC-2) to Vcc
22. Click on 'Next' button to Connect Q-3 (Q-2 of IC-2) to 7-Seg Display
23. Click on 'Next' button to Connect Q-1 to Input-1 of NAND Gate
24. Click on 'Next' button to Connect Q-3 to Input-2 of NAND Gate
25. Click on 'Next' button to Connect Output of NAND Gate to CLEAR-0
26. Click on 'Next' button to Connect Output of NAND Gate to CLEAR-1
27. Click on 'Next' button to Connect Output of NAND Gate to CLEAR-2
28. Click on 'Next' button to Connect Output of NAND Gate to CLEAR-3

Block Diagram

ICs used in this circuit with pin diagram

74LS00

No preview

74LS00

Quad 2-input NAND Gates

74LS76

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74LS76

Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs

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