5.Quad 2-Input NAND Gates with Open-Collector Outputs

Sayyedain Abbas
Sayyedain Abbas
• Created on Sep 17, 2025 • 0 • 0 • 1
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5.Quad 2-Input NAND Gates with Open-Collector Outputs
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Integrated Circuits Used

74LS00

Procedure

  1. Add IC 74LS00 into ICBase-2 (74LS00).
  2. Connect Pin-1 (Input) of ICBase-2 (74LS00) to Input-0.
  3. Connect Input-1 to Pin-2 (Input) of ICBase-2 (74LS00).
  4. Connect Pin-4 (Input) of ICBase-2 (74LS00) to Input-2.
  5. Connect Input-3 to Pin-5 (Input) of ICBase-2 (74LS00).
  6. Connect Pin-7 (Ground) of ICBase-2 (74LS00) to GND Port.
  7. Connect Output-0 to Pin-6 (Output) of ICBase-2 (74LS00).
  8. Connect Pin-3 (Output) of ICBase-2 (74LS00) to Output-1.
  9. Connect Pin-20 (VCC) of ICBase-2 (74LS00) to VCC Port.
  10. Connect Input-4 to Pin-15 (Input) of ICBase-2 (74LS00).
  11. Connect Pin-16 (Input) of ICBase-2 (74LS00) to Input-5.
  12. Connect Input-6 to Pin-18 (Input) of ICBase-2 (74LS00).
  13. Connect Pin-19 (Input) of ICBase-2 (74LS00) to Input-7.