Parity Genrator

Anurag
Anurag Nage
• Created on Apr 24, 2025 • 0 • 0 • 1
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Parity Genrator
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Integrated Circuits Used

74LS86

Description

IC : 74LS86

Procedure

  1. Add IC 74LS86 into ICBase-1 (74LS86).
  2. Add IC 74LS86 into ICBase-2 (74LS86).
  3. Connect Pin-20 (VCC) of ICBase-2 (74LS86) to VCC Port.
  4. Connect Pin-20 (VCC) of ICBase-1 (74LS86) to VCC Port.
  5. Connect Pin-7 (Ground) of ICBase-2 (74LS86) to GND Port.
  6. Connect Pin-7 (Ground) of ICBase-1 (74LS86) to GND Port.
  7. Connect Pin-1 (Input) of ICBase-1 (74LS86) to Input-15.
  8. Connect Pin-2 (Input) of ICBase-1 (74LS86) to Input-14.
  9. Connect Pin-1 (Input) of ICBase-2 (74LS86) to Input-13.
  10. Connect Pin-2 (Input) of ICBase-2 (74LS86) to Pin-3 (Output) of ICBase-1 (74LS86).
  11. Connect Output-10 to Pin-3 (Output) of ICBase-2 (74LS86).