Optimized D Latch

Suvarna
Suvarna G
• Created on Dec 9, 2023 • 0 • 0 • 1
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Optimized D Latch
100%

Integrated Circuits Used

74LS00

Description

Less number of gates as compared to the usual one

Procedure

  1. Connect Pin-1 (Input) of ICBase-1 (74LS00) to Input-0.
  2. Connect Pin-2 (Input) of ICBase-1 (74LS00) to Input-1.
  3. Connect Pin-19 (Input) of ICBase-1 (74LS00) to Pin-3 (Output) of ICBase-1 (74LS00).
  4. Connect Output-1 to Pin-18 (Input) of ICBase-1 (74LS00).
  5. Connect Pin-14 (Output) of ICBase-1 (74LS00) to Pin-18 (Input) of ICBase-1 (74LS00).
  6. Connect Output-0 to Pin-17 (Output) of ICBase-1 (74LS00).
  7. Connect Pin-15 (Input) of ICBase-1 (74LS00) to Pin-17 (Output) of ICBase-1 (74LS00).
  8. Connect Pin-4 (Input) of ICBase-1 (74LS00) to Input-0.
  9. Connect Pin-5 (Input) of ICBase-1 (74LS00) to Pin-3 (Output) of ICBase-1 (74LS00).
  10. Connect Pin-16 (Input) of ICBase-1 (74LS00) to Pin-6 (Output) of ICBase-1 (74LS00).
  11. Connect VCC Port to Pin-20 (VCC) of ICBase-1 (74LS00).
  12. Connect GND Port to Pin-7 (Ground) of ICBase-1 (74LS00).
  13. Add IC 74LS00 into ICBase-1 (74LS00).