JK TO SR FLIP FLOP

Shardool
Shardool Patil
• Created on Oct 27, 2023 • 0 • 0 • 1
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JK TO SR FLIP FLOP
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Integrated Circuits Used

74LS00

Description

USING NAND GATES

Procedure

  1. Add IC 74LS00 into ICBase-1 (74LS00).
  2. Add IC 74LS00 into ICBase-2 (74LS00).
  3. Connect Pin-1 (Input) of ICBase-1 (74LS00) to Input-15.
  4. Connect Pin-4 (Input) of ICBase-1 (74LS00) to Input-14.
  5. Connect Pin-2 (Input) of ICBase-1 (74LS00) to Clock port of 1Hz frequency.
  6. Connect Pin-5 (Input) of ICBase-1 (74LS00) to Clock port of 1Hz frequency.
  7. Connect Pin-1 (Input) of ICBase-2 (74LS00) to Pin-3 (Output) of ICBase-1 (74LS00).
  8. Connect Pin-4 (Input) of ICBase-2 (74LS00) to Pin-6 (Output) of ICBase-1 (74LS00).
  9. Connect Pin-5 (Input) of ICBase-2 (74LS00) to Pin-3 (Output) of ICBase-2 (74LS00).
  10. Connect Pin-2 (Input) of ICBase-2 (74LS00) to Pin-6 (Output) of ICBase-2 (74LS00).
  11. Connect Output-15 to Pin-3 (Output) of ICBase-2 (74LS00).
  12. Connect Output-14 to Pin-6 (Output) of ICBase-2 (74LS00).
  13. Connect GND Port to Pin-7 (Ground) of ICBase-1 (74LS00).
  14. Connect Pin-7 (Input & Output) of ICBase-3 to GND Port.
  15. Connect GND Port to Pin-7 (Ground) of ICBase-2 (74LS00).
  16. Connect Pin-20 (Input & Output) of ICBase-3 to VCC Port.
  17. Connect Pin-20 (VCC) of ICBase-2 (74LS00) to VCC Port.
  18. Connect Pin-20 (VCC) of ICBase-1 (74LS00) to VCC Port.