SR FF

Jaydeep
Jaydeep Palve
Created on Oct 27, 2023 0 0 2
SR FF
100%

Integrated Circuits Used

Description

INPUT 0-S 1-R OUTPUT 0-Qn

Procedure

  1. Add IC 74LS00 into ICBase-1 (74LS00).
  2. Add IC 74LS10 into ICBase-2 (74LS10).
  3. Connect VCC Port to Pin-20 (VCC) of ICBase-1 (74LS00).
  4. Connect GND Port to Pin-7 (Ground) of ICBase-1 (74LS00).
  5. Connect Pin-6 (Output) of ICBase-1 (74LS00) to Pin-2 (Input) of ICBase-1 (74LS00).
  6. Connect Pin-5 (Input) of ICBase-1 (74LS00) to Pin-3 (Output) of ICBase-1 (74LS00).
  7. Connect Output-0 to Pin-3 (Output) of ICBase-1 (74LS00).
  8. Connect VCC Port to Pin-20 (VCC) of ICBase-2 (74LS10).
  9. Connect GND Port to Pin-7 (Ground) of ICBase-2 (74LS10).
  10. Connect Pin-19 (Input) of ICBase-1 (74LS00) to Input-0.
  11. Connect VCC Port to Pin-18 (Input) of ICBase-1 (74LS00).
  12. Connect Pin-1 (Input) of ICBase-1 (74LS00) to Pin-17 (Output) of ICBase-1 (74LS00).
  13. Connect Pin-16 (Input) of ICBase-1 (74LS00) to Input-1.
  14. Connect Pin-15 (Input) of ICBase-1 (74LS00) to VCC Port.
  15. Connect Pin-4 (Input) of ICBase-1 (74LS00) to Pin-14 (Output) of ICBase-1 (74LS00).