SR flipflop using and gate

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• Created on Mar 21, 2023 • 0 • 0 • 1
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SR flipflop using and gate
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Integrated Circuits Used

74LS00

Description

opposite of nor ff in sr flip flop we use clk truth table --------------------- clk s r | q 0 x x | memory 1 0 0 | memory 1 0 1 | 0 1 1 0 | 1

Procedure

  1. Connect VCC Port to Pin-20 (VCC) of ICBase-2 (74LS00).
  2. Connect GND Port to Pin-7 (Ground) of ICBase-2 (74LS00).
  3. Connect Pin-6 (Output) of ICBase-2 (74LS00) to Pin-2 (Input) of ICBase-2 (74LS00).
  4. Connect Pin-5 (Input) of ICBase-2 (74LS00) to Pin-3 (Output) of ICBase-2 (74LS00).
  5. Connect Output-15 to Pin-3 (Output) of ICBase-2 (74LS00).
  6. Connect Output-14 to Pin-6 (Output) of ICBase-2 (74LS00).
  7. Add IC 74LS00 into ICBase-2 (74LS00).
  8. Connect Input-13 to Pin-19 (Input) of ICBase-2 (74LS00).
  9. Connect Input-12 to Pin-16 (Input) of ICBase-2 (74LS00).
  10. Connect Pin-1 (Input) of ICBase-2 (74LS00) to Pin-17 (Output) of ICBase-2 (74LS00).
  11. Connect Pin-18 (Input) of ICBase-2 (74LS00) to Clock port of 1Hz frequency.
  12. Connect Pin-15 (Input) of ICBase-2 (74LS00) to Clock port of 1Hz frequency.
  13. Connect Pin-4 (Input) of ICBase-2 (74LS00) to Pin-14 (Output) of ICBase-2 (74LS00).