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Aarizkhan Shaikh
DR. VISHWANATH KARAD MIT WORLD PEACE UNIVERSITY, PUNE • Computer
17 Circuits
LAB - 3.1
Aarizkhan Shaikh
0
0
May 7, 2023
74LS151
LAB - 2
Aarizkhan Shaikh
0
0
May 7, 2023
74LS86
LAB - 1
Aarizkhan Shaikh
0
0
May 7, 2023
74LS08
74LS32
74LS04
74LS86
2-bit ASYNC UP counter
Aarizkhan Shaikh
0
0
Mar 21, 2023
74LS76
3-bit ASYNC UP Counter
Aarizkhan Shaikh
0
0
Mar 21, 2023
74LS76
3-bit ASYNC DOWN Counter
Aarizkhan Shaikh
0
0
Mar 21, 2023
74LS76
2-bit Async DOWN Counter
Aarizkhan Shaikh
0
0
Mar 21, 2023
74LS76
7476 - MS JK Flip - Flop (Truth Table Veri.)
Aarizkhan Shaikh
0
0
Mar 14, 2023
74LS76
T Flip Flop
Aarizkhan Shaikh
0
0
Mar 14, 2023
74LS76
Delay Flip Flop
Aarizkhan Shaikh
0
0
Mar 14, 2023
74LS76
74LS04
Half Adder using Basic Logic Gates (XOR, AND)
Aarizkhan Shaikh
0
0
Feb 26, 2023
74LS86
74LS08
Half Sub using logic gates (and,not,etc..)
Aarizkhan Shaikh
0
0
Feb 26, 2023
74LS86
74LS04
74LS08
Full Adder using 2 8:1 MUX
Aarizkhan Shaikh
0
0
Feb 26, 2023
74LS151
Full Sub using MUX 2 8:1
Aarizkhan Shaikh
0
0
Feb 26, 2023
74LS151
Truth Table for MUX lab-3
Aarizkhan Shaikh
0
0
Jan 31, 2023
74LS151
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