Veer Hinglajia

DR. VISHWANATH KARAD MIT WORLD PEACE UNIVERSITY, PUNE • Computer

40 Circuits

Y= AB + B'C +AC

Y= AB + B'C +AC

74LS04 74LS08 74LS32 74LS11

FULL ADDER

FULL ADDER

74LS86 74LS32 74LS08

8:1 using 2 4:1 MUX active low

8:1 using 2 4:1 MUX active low

74LS153 74LS32 74LS04

SOP corrected 3 bit

SOP corrected 3 bit

Delay Flip Flop

Delay Flip Flop

MOD 10 Decade counter

MOD 10 Decade counter

FULL SUBTRACTOR

FULL SUBTRACTOR

Toggle flip flop

Toggle flip flop

Full subtractor using mux

Full subtractor using mux

Half adder using NAND gates

Half adder using NAND gates

2 bit async down

2 bit async down

3 bit async up

3 bit async up

MOD6 counter

MOD6 counter

mod 100

mod 100

3 bit async down

3 bit async down

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