Piamonte_ECE3A_F1_CPE-LOG Lab

Christel
Christel Piamonte
• Created on Oct 13, 2022 • 0 • 0 • 3
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Piamonte_ECE3A_F1_CPE-LOG Lab
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Integrated Circuits Used

74LS21 74LS04 74LS32

Description

C' + AB'CD'

Procedure

  1. Add IC 74LS21 into ICBase-3 (74LS21).
  2. Add IC 74LS04 into ICBase-2 (74LS04).
  3. Add IC 74LS32 into ICBase-4 (74LS32).
  4. Connect Pin-1 (Input) of ICBase-3 (74LS21) to Input-3.
  5. Connect Pin-19 (Input) of ICBase-2 (74LS04) to Input-2.
  6. Connect Pin-2 (Input) of ICBase-3 (74LS21) to Pin-18 (Output) of ICBase-2 (74LS04).
  7. Connect Pin-15 (Input) of ICBase-2 (74LS04) to Input-0.
  8. Connect Pin-4 (Input) of ICBase-3 (74LS21) to Input-1.
  9. Connect Pin-5 (Input) of ICBase-3 (74LS21) to Pin-14 (Output) of ICBase-2 (74LS04).
  10. Connect Pin-17 (Input) of ICBase-2 (74LS04) to Input-1.
  11. Connect Pin-1 (Input) of ICBase-4 (74LS32) to Pin-16 (Output) of ICBase-2 (74LS04).
  12. Connect Pin-2 (Input) of ICBase-4 (74LS32) to Pin-6 (Output) of ICBase-3 (74LS21).
  13. Connect Output-0 to Pin-3 (Output) of ICBase-4 (74LS32).
  14. Connect Pin-7 (Ground) of ICBase-2 (74LS04) to GND Port.
  15. Connect Pin-7 (Ground) of ICBase-3 (74LS21) to GND Port.
  16. Connect Pin-7 (Ground) of ICBase-4 (74LS32) to GND Port.
  17. Connect Pin-20 (VCC) of ICBase-2 (74LS04) to VCC Port.
  18. Connect Pin-20 (VCC) of ICBase-3 (74LS21) to VCC Port.
  19. Connect Pin-20 (VCC) of ICBase-4 (74LS32) to VCC Port.