5.2 NAND MAjority logic

Kyla Nicole
Kyla Nicole Del Mundo
• Created on Nov 14, 2022 • 0 • 0 • 2
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5.2 NAND MAjority logic
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Integrated Circuits Used

74LS00 74LS10

Procedure

  1. Add IC 74LS00 into ICBase-2 (74LS00).
  2. Add IC 74LS10 into ICBase-3 (74LS10).
  3. Connect Output-1 to Pin-18 (Output) of ICBase-3 (74LS10).
  4. Connect Pin-20 (VCC) of ICBase-3 (74LS10) to VCC Port.
  5. Connect VCC Port to Pin-20 (VCC) of ICBase-2 (74LS00).
  6. Connect GND Port to Pin-7 (Ground) of ICBase-3 (74LS10).
  7. Connect GND Port to Pin-7 (Ground) of ICBase-2 (74LS00).
  8. Connect Input-2 to Pin-1 (Input) of ICBase-2 (74LS00).
  9. Connect Input-3 to Pin-2 (Input) of ICBase-2 (74LS00).
  10. Connect Pin-19 (Input) of ICBase-3 (74LS10) to Pin-3 (Output) of ICBase-2 (74LS00).
  11. Connect Input-1 to Pin-4 (Input) of ICBase-2 (74LS00).
  12. Connect Input-3 to Pin-5 (Input) of ICBase-2 (74LS00).
  13. Connect Pin-1 (Input) of ICBase-3 (74LS10) to Pin-6 (Output) of ICBase-2 (74LS00).
  14. Connect Input-1 to Pin-18 (Input) of ICBase-2 (74LS00).
  15. Connect Input-2 to Pin-19 (Input) of ICBase-2 (74LS00).
  16. Connect Pin-2 (Input) of ICBase-3 (74LS10) to Pin-17 (Output) of ICBase-2 (74LS00).