NAND

jolie kris
jolie kris briton
• Created on May 13, 2022 • 0 • 0 • 1
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NAND
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Integrated Circuits Used

74LS00

Description

NAND GATES

Procedure

  1. Connect Pin-20 (VCC) of ICBase-3 (74LS00) to VCC Port.
  2. Connect Input-0 to Pin-1 (Input) of ICBase-3 (74LS00).
  3. Connect GND Port to Pin-7 (Ground) of ICBase-3 (74LS00).
  4. Connect VCC Port to Clock port of 5Hz frequency.
  5. Connect Pin-2 (Input) of ICBase-3 (74LS00) to Pin-6 (Output) of ICBase-3 (74LS00).
  6. Connect Pin-3 (Output) of ICBase-3 (74LS00) to Pin-4 (Input) of ICBase-3 (74LS00).
  7. Connect Input-1 to Pin-5 (Input) of ICBase-3 (74LS00).
  8. Connect Output-0 to Pin-3 (Output) of ICBase-3 (74LS00).
  9. Connect Output-1 to Pin-6 (Output) of ICBase-3 (74LS00).
  10. Add IC 74LS00 into ICBase-3 (74LS00).