RUCHITHA .BM 4MC20CS125 LAB EXP 7

Pooja
Pooja S
• Created on Jan 7, 2022 • 0 • 0 • 1
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RUCHITHA .BM 4MC20CS125 LAB EXP 7
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Integrated Circuits Used

74LS86

Description

PARITY CHECKER AND GENERATOR

Procedure

  1. Add IC 74LS86 into ICBase-1 (74LS86).
  2. Connect Input-15 to Pin-1 (Input) of ICBase-1 (74LS86).
  3. Connect Input-14 to Pin-2 (Input) of ICBase-1 (74LS86).
  4. Connect Pin-15 (Input) of ICBase-1 (74LS86) to Pin-3 (Output) of ICBase-1 (74LS86).
  5. Connect Input-13 to Pin-4 (Input) of ICBase-1 (74LS86).
  6. Connect Input-12 to Pin-5 (Input) of ICBase-1 (74LS86).
  7. Connect Pin-16 (Input) of ICBase-1 (74LS86) to Pin-6 (Output) of ICBase-1 (74LS86).
  8. Connect GND Port to Pin-7 (Ground) of ICBase-1 (74LS86).
  9. Connect VCC Port to Pin-20 (VCC) of ICBase-1 (74LS86).
  10. Connect Output-4 to Pin-14 (Output) of ICBase-1 (74LS86).