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Devarshi Mahajan
Dr. D.Y. Patil Institute of Engineering, Management and Research • Computer
36 Circuits
JK Master Slave Flip Flop
Devarshi Mahajan
0
0
Dec 13, 2021
74LS10
74LS00
Sequence Generator using JK Flip Flop
Devarshi Mahajan
0
0
Dec 13, 2021
74LS76
74LS08
74LS32
Ring Counter
Devarshi Mahajan
0
0
Dec 12, 2021
74LS74
Johnson Ring Counter
Devarshi Mahajan
0
0
Dec 12, 2021
74LS74
Half Subtractor using Nand Gate
Devarshi Mahajan
0
0
Dec 12, 2021
74LS00
SR to JK logic
Devarshi Mahajan
0
0
Dec 12, 2021
74LS10
74LS00
SR to JK
Devarshi Mahajan
0
0
Dec 12, 2021
74LS76
Parity Generator
Devarshi Mahajan
0
0
Dec 12, 2021
74LS86
74LS04
Parity Checker
Devarshi Mahajan
0
0
Dec 12, 2021
74LS86
74LS04
SR to T logic
Devarshi Mahajan
0
0
Dec 12, 2021
74LS00
SR to D logic
Devarshi Mahajan
0
0
Dec 12, 2021
74LS00
74LS04
2:4 DECODER (MAX TERM GENERATOR)
Devarshi Mahajan
0
0
Dec 12, 2021
74LS00
2:4 DECODER (MIN TERM GENERATOR)
Devarshi Mahajan
0
0
Dec 12, 2021
74LS04
74LS08
Full adder using Basic Gates
Devarshi Mahajan
0
0
Dec 9, 2021
74LS86
74LS08
74LS32
Half adder using Nand gates
Devarshi Mahajan
0
0
Dec 9, 2021
74LS00
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