CHECKER AND PARITY GENERATOR

Shraddha
Shraddha Bansode
Created on Sep 21, 2021 0 0 1
CHECKER AND PARITY GENERATOR
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Integrated Circuits Used

Procedure

  1. Add IC 74LS86 into ICBase-1 (74LS86).
  2. Connect VCC Port to Pin-20 (VCC) of ICBase-1 (74LS86).
  3. Connect GND Port to Pin-7 (Ground) of ICBase-1 (74LS86).
  4. Connect Input-12 to Pin-1 (Input) of ICBase-1 (74LS86).
  5. Connect Input-11 to Pin-2 (Input) of ICBase-1 (74LS86).
  6. Connect Pin-15 (Input) of ICBase-1 (74LS86) to Pin-3 (Output) of ICBase-1 (74LS86).
  7. Connect Input-10 to Pin-4 (Input) of ICBase-1 (74LS86).
  8. Connect Input-9 to Pin-5 (Input) of ICBase-1 (74LS86).
  9. Connect Pin-14 (Output) of ICBase-1 (74LS86) to Output-9.
  10. Add IC 74LS86 into ICBase-2 (74LS86).
  11. Connect Input-2 to Pin-1 (Input) of ICBase-2 (74LS86).
  12. Connect Pin-6 (Output) of ICBase-2 (74LS86) to Pin-2 (Input) of ICBase-2 (74LS86).
  13. Connect Output-2 to Pin-3 (Output) of ICBase-2 (74LS86).
  14. Connect Input-1 to Pin-4 (Input) of ICBase-2 (74LS86).
  15. Connect Input-0 to Pin-5 (Input) of ICBase-2 (74LS86).
  16. Connect GND Port to Pin-7 (Ground) of ICBase-2 (74LS86).
  17. Connect VCC Port to Pin-20 (VCC) of ICBase-2 (74LS86).