Affan Sayed

DR. VISHWANATH KARAD MIT WORLD PEACE UNIVERSITY, PUNE • Computer

21 Circuits

seq(without)

seq(without)

seq detector

seq detector

74LS76 74LS08 74LS04

FULL ADDER USING DECODER

FULL ADDER USING DECODER

FULL ADDER USING DECODER

FULL ADDER USING DECODER

MOD-5 ASYNCHRONOUS UP COUNTER

MOD-5 ASYNCHRONOUS UP COUNTER

FULL ADDER USING 4:1 DECODER

FULL ADDER USING 4:1 DECODER

4:1 MUX USING MUX REDUCTION

4:1 MUX USING MUX REDUCTION

SOP (m=0,3)

SOP (m=0,3)

POS(M=0,3)

POS(M=0,3)

Half Adder

Half Adder

8:1 MUX USING 2 4:1 MUX

8:1 MUX USING 2 4:1 MUX

74LS153 74LS04 74LS32

GRAY TO BINARY

GRAY TO BINARY

BINARY TO GRAY

BINARY TO GRAY

MOD-8 ASYNCHRONOUS DOWN COUNTER

MOD-8 ASYNCHRONOUS DOWN COUNTER

MOD 8 ASYNCHRONOUS UP COUNTER

MOD 8 ASYNCHRONOUS UP COUNTER

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