Ankita Markad

DR. VISHWANATH KARAD MIT WORLD PEACE UNIVERSITY, PUNE • Computer

28 Circuits

reduction method: SOP m(0,1,3,5,6)

reduction method: SOP m(0,1,3,5,6)

half adder(XOR) - 8:1 using 4:1

half adder(XOR) - 8:1 using 4:1

74LS153 74LS04 74LS32

mux: SOP/POS of m(0,3)

mux: SOP/POS of m(0,3)

mod6

mod6

Ex-OR Gate Grey code to Binary code - Copy

Ex-OR Gate Grey code to Binary code - Copy

Lab1 Ex-OR Gate - Copy

Lab1 Ex-OR Gate - Copy

FF down/up counter

FF down/up counter

mux: both sop/pos

mux: both sop/pos

AND/OR/NOT gates - Copy

AND/OR/NOT gates - Copy

74LS08 74LS32 74LS04

gray to binary

gray to binary

binary to gray

binary to gray

AND Circuit - Copy

AND Circuit - Copy

AND/OR/NOT gates

AND/OR/NOT gates

74LS08 74LS32 74LS04

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