Priyal Agrawal

DR. VISHWANATH KARAD MIT WORLD PEACE UNIVERSITY, PUNE • Computer

51 Circuits

full adder using mux new

full adder using mux new

74LS153 74LS04 74LS32

Full Adder using 8:1 Mux Final

Full Adder using 8:1 Mux Final

74LS153 74LS04 74LS32

full adder using decoder

full adder using decoder

MUX 8:1 using 4:1

MUX 8:1 using 4:1

74LS04 74LS153 74LS32

full adder using reduction

full adder using reduction

4:16 decoder using 3:8

4:16 decoder using 3:8

4:1 sop pos verification

4:1 sop pos verification

SOP POS final

SOP POS final

Reduction Method

Reduction Method

final of 8:1 using 4:1

final of 8:1 using 4:1

74LS153 74LS04 74LS32

Half Adder and only Multiplexer

Half Adder and only Multiplexer

4:1 FINAL

4:1 FINAL

4:1 - Copy - Copy

4:1 - Copy - Copy

74LS153 74LS32 74LS04

half adder using 4:1 mux FINAL

half adder using 4:1 mux FINAL

8:1 MUX USING 4:1

8:1 MUX USING 4:1

74LS153 74LS32 74LS00

Page 3