Ayushi Prasad

DR. VISHWANATH KARAD MIT WORLD PEACE UNIVERSITY, PUNE • Computer

26 Circuits

mod 8 - 3 bit Asynchronous UP/DOWN counter (1 FF)

mod 8 - 3 bit Asynchronous UP/DOWN counter (1 FF)

3-bit Synchronous Up Counter

3-bit Synchronous Up Counter

1 Assignment 3

1 Assignment 3

Assignment 3

Assignment 3

4th Case Hardware Reduction Table Design and Implement Combinational Logic Design using MUX/Decoders ICs

4th Case Hardware Reduction Table Design and Implement Combinational Logic Design using MUX/Decoders ICs

3rd Case Half-Adder Design and Implement Combinational Logic Design using MUX/Decoders ICs

3rd Case Half-Adder Design and Implement Combinational Logic Design using MUX/Decoders ICs

2nd Case SOP & POS Design and Implement Combinational Logic Design using MUX/Decoder ICs

2nd Case SOP & POS Design and Implement Combinational Logic Design using MUX/Decoder ICs

Design and Implement combinational logic design using MUX/Decoder ICs

Design and Implement combinational logic design using MUX/Decoder ICs

4-bit Binary to Gray Code Converter

4-bit Binary to Gray Code Converter

4-bit Gray to Binary Converter

4-bit Gray to Binary Converter

Binary to Gray Code Converter

Binary to Gray Code Converter

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