Vaidehi Sinha

DR. VISHWANATH KARAD MIT WORLD PEACE UNIVERSITY, PUNE • Computer

28 Circuits

Lab 5

Lab 5

74LS76 74LS86 74LS08 74LS32 74LS04

Lab - Mealy - 5

Lab - Mealy - 5

74LS76 74LS04 74LS08

Lab 6

Lab 6

Lab4 - 3 Bit Synchronous Down

Lab4 - 3 Bit Synchronous Down

Lab2 - 3:8 Decoder

Lab2 - 3:8 Decoder

Lab2 - 8:1 using 4:1

Lab2 - 8:1 using 4:1

74LS153 74LS04 74LS32

Lab2 - 8:1 using 4:1 (Reduction)

Lab2 - 8:1 using 4:1 (Reduction)

Lab2 - Full Adder Using 3:8 Decoder

Lab2 - Full Adder Using 3:8 Decoder

Lab2-Half Adder

Lab2-Half Adder

Lab2-POS-0,3

Lab2-POS-0,3

Lab2 - SOP - 0,3

Lab2 - SOP - 0,3

Lab4 - 3 Bit Synchronous Up/Down Counter

Lab4 - 3 Bit Synchronous Up/Down Counter

Lab3 - Mod5 -UP

Lab3 - Mod5 -UP

Lab 3 - Mod8 - Up/Down

Lab 3 - Mod8 - Up/Down

Lab1 - Binary to Gray

Lab1 - Binary to Gray

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