2 Bit sync up counter

Arnav
Arnav Deshpande
• Created on Sep 23, 2021 • 0 • 0 • 1
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2 Bit sync up counter
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Integrated Circuits Used

74LS76

Description

DE Lab examination

Procedure

  1. Add IC 74LS76 into ICBase-3 (74LS76).
  2. Connect VCC Port to Pin-5 (VCC) of ICBase-3 (74LS76).
  3. Connect GND Port to Pin-17 (Ground) of ICBase-3 (74LS76).
  4. Connect Clock port of 1Hz frequency to Pin-1 (Input) of ICBase-3 (74LS76).
  5. Connect Clock port of 1Hz frequency to Pin-6 (Input) of ICBase-3 (74LS76).
  6. Connect Pin-4 (Input) of ICBase-3 (74LS76) to Pin-15 (Output) of ICBase-3 (74LS76).
  7. Connect Pin-20 (Input) of ICBase-3 (74LS76) to Pin-15 (Output) of ICBase-3 (74LS76).
  8. Connect VCC Port to Pin-16 (Input) of ICBase-3 (74LS76).
  9. Connect VCC Port to Pin-13 (Input) of ICBase-3 (74LS76).
  10. Connect VCC Port to Pin-2 (Input) of ICBase-3 (74LS76).
  11. Connect VCC Port to Pin-3 (Input) of ICBase-3 (74LS76).
  12. Connect VCC Port to Pin-7 (Input) of ICBase-3 (74LS76).
  13. Connect VCC Port to Pin-8 (Input) of ICBase-3 (74LS76).
  14. Connect Seven segment display 1 to Pin-19 (Output) of ICBase-3 (74LS76).
  15. Connect Seven segment display 1 to Pin-15 (Output) of ICBase-3 (74LS76).