Sarthak Bindal

INDIAN INSTITUTE OF INFORMATION TECHNOLOGY KOTTAYAM • Computer

21 Circuits

3 bit gray code to binary code

3 bit gray code to binary code

De-Morgan's Law Verification

De-Morgan's Law Verification

74LS08 74LS04 74LS32

3 bit 2's complementor

3 bit 2's complementor

74LS08 74LS04 74LS32 74LS11

Minterm using NAND Gate

Minterm using NAND Gate

74LS10 74LS04 74LS20 74LS00

SR Latch using NOR gates

SR Latch using NOR gates

Single bit comparator

Single bit comparator

74LS04 74LS08 74LS02

Half Adder using NOR Gates

Half Adder using NOR Gates

1:2 De-Multiplexer using logic gates

1:2 De-Multiplexer using logic gates

4:1 MUX

4:1 MUX

74LS04 74LS11 74LS32

2:4 DECODER

2:4 DECODER

2:1 MUX

2:1 MUX

74LS08 74LS04 74LS32

XNOR GATE using basic gates

XNOR GATE using basic gates

74LS08 74LS04 74LS32

AND Circuit verification

AND Circuit verification

NOR Gate verification

NOR Gate verification

74LS02 74LS32 74LS04

74LS08 - AND -bindalSarthak - Copy - Copy

74LS08 - AND -bindalSarthak - Copy - Copy

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