SR latch with NAND gates

Vansh
Vansh Jagyasi
• Created on Jul 7, 2021 • 0 • 0 • 2
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SR latch with NAND gates
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Integrated Circuits Used

74LS00 74LS04

Procedure

  1. Add IC 74LS00 into ICBase-1 (74LS00).
  2. Add IC 74LS04 into ICBase-2 (74LS04).
  3. Connect Pin-1 (Input) of ICBase-2 (74LS04) to Input-0.
  4. Connect Pin-3 (Input) of ICBase-2 (74LS04) to Input-1.
  5. Connect Pin-1 (Input) of ICBase-1 (74LS00) to Pin-2 (Output) of ICBase-2 (74LS04).
  6. Connect Pin-4 (Input) of ICBase-1 (74LS00) to Pin-4 (Output) of ICBase-2 (74LS04).
  7. Connect Pin-5 (Input) of ICBase-1 (74LS00) to Pin-3 (Output) of ICBase-1 (74LS00).
  8. Connect Pin-2 (Input) of ICBase-1 (74LS00) to Pin-6 (Output) of ICBase-1 (74LS00).
  9. Connect Output-0 to Pin-3 (Output) of ICBase-1 (74LS00).
  10. Connect Output-1 to Pin-6 (Output) of ICBase-1 (74LS00).
  11. Connect GND Port to Pin-7 (Ground) of ICBase-1 (74LS00).
  12. Connect GND Port to Pin-7 (Ground) of ICBase-2 (74LS04).
  13. Connect VCC Port to Pin-20 (VCC) of ICBase-2 (74LS04).
  14. Connect VCC Port to Pin-20 (VCC) of ICBase-1 (74LS00).